The Chimera™ SDK
The Chimera SDK compiles your model onto a single programmable core — the entire graph, not just the operators a fixed-function block happens to support. New operators, custom kernels, next year's architectures: all run at native speed, because the compiler decides what runs, not the silicon.
The developer journey
Bring a trained ONNX model out of PyTorch or TensorFlow. Quantize it with quadric_quantize, then compile, simulate, validate, and profile against a cycle-approximate (±5%) model of the core — in the Chimera SDK, on-prem or in your cloud. No board required.
onnxquadric_quantizejob.compileISSprint(job)from tvm.contrib.epu.chimera_job.quantize import quadric_quantize
from tvm.contrib.epu.chimera_job.chimera_job import ChimeraJob
from tvm.contrib.epu.chimera_job.hw_config import HWConfig
q = quadric_quantize(
floating_point_model_path="model.onnx",
num_images=20, calibration_folder="./calib")
hw = HWConfig(product="QC-U", num_cores=4)
job = ChimeraJob(q.onnx_path, hw_config=hw)
job.compile() # CGC -> CCL C++ -> LLVM
job.run_inference_harness() # cycle-approximate ISS
job.validate_ort_iss() # accuracy vs ONNX Runtime
print(job) # FPS, power, MAC util, cyclesQuantized ≠ degraded
validate_ort_iss scores the simulator's INT8 output against ONNX Runtime's float output — on your model, before you commit. In our Whisper-Tiny reference notebook that correlation is near-perfect (0.9998); run the same check on yours and see the delta, not a promise.
The graph compiler
The Chimera Graph Compiler ingests your ONNX graph and does the hard part — operator fusion, re-quantization rescheduling to hold precision where it matters, tensor layout across DDR / L2 / local memory, predictive weight prefetch, and multicore code generation. What it emits isn't a sealed binary. It's human-readable C++ built on our Chimera Compute Library — code you can open, run with a one-line CLI, and hand-tune. CGC is built on Apache TVM; the datapath it targets is 100% programmable.
Chimera Graph Compiler — ONNX to Chimera ISA
print(job) profile: latency · FPS · power · MAC util · cycles.Extend it yourself
On a fixed-function accelerator, an unsupported operator falls back to a general-purpose CPU or DSP — a dramatic drop in throughput — or you wait a release cycle for the vendor to add it, then hope. That's the tax behind every “custom operators supported” footnote in this category.
Here, you write the operator. Express it in C++ with the Chimera Compute Library, splice it into the graph with a few lines, and it runs at full speed on the same parallel core as every native operator — no second engine, no data shuffled between cores.
from tvm.contrib.epu import graphutils as gutils
replacer = gutils.CustomOpReplacer(onnx.load("model.onnx"))
subgraph, model = replacer.replace_subgraph(
output_nodes=["postprocess_output"],
input_nodes=["boxes", "scores"],
ccl_func_name="user::customPostProcess")// your kernel: full access to the PE array, LRM, DMA
template <typename T>
void customPostProcess(const T* in, T* out, size_t n) {
// runs native-speed on the same core as every op
...
}Your custom op on Chimera
Full PE array, native speed
Same core as every native operator — no second engine, no data copied between cores.
The same op on a fixed-function NPU
Falls back to a CPU / DSP
By Quadric's datasheet framing, that fallback is up to a ~1000× slowdown, plus the cost of moving data between cores.
New custom operators run as fast as native operators. That is the whole point of a programmable core.
The living compiler
A hardwired accelerator freezes its operator set the day it's taped out — so it “breaks” on the architecture nobody had invented yet. A Chimera core is a programmable processor, so its model coverage keeps growing through compiler releases, on hardware already in the field. This isn't a promise; it's our release history. And it reaches backward too: code written for the prior QB-generation cores recompiles and runs on today's QC cores — so your software outlives a silicon generation.
Llama-2
first LLM on the GPNPU
+ any-convolution support
ConvNeXt
QC-series target
detection + segmentation zoos
PointPillars
3D perception — LiDAR + monocular
+ classifier & OCR zoos
Qwen3-8B
+ DeepSeek-R1-Distill
billion-scale, 4-bit weights
Vision Transformer
Swin attention
+ deformable attention
pi0.5 VLA
vision-language-action
+ Whisper, BEVFormer 3D
Simulate & profile
The Chimera Instruction Set Simulator models the whole core to within ±5%, with per-workload power estimation and full state visibility — deterministic and inspectable, not a black-box engine build that changes its answer between runs. Run it standalone to tune a kernel, or drop it into a SystemC virtual prototype of your full SoC to see real memory-system behavior.
Cycle breakdown
Where every cycle goes: compute vs MAC vs data movement.
Average power
A per-workload power estimate from the ISS — before there's silicon or a board.
External bandwidth
DDR traffic the compiler worked to avoid.
FILM region (fusion-in-local-memory)
Intermediates kept on-chip, off DDR.
Model coverage
Classifiers, detectors, segmentation, pose, 3D perception, vision transformers, LLMs, and vision-language-action stacks all compile from the same toolchain. Every benchmark is live — FPS, FPS/W, and a full cycle breakdown per model and target, straight from DevStudio.
Image classification
ResNet · ViT · ConvNeXt · EfficientNet
Object detection
YOLO · RetinaNet · FCOS · DETR
Segmentation
YOLOP · UNet · HRNet · FCN
Pose estimation
RSN · top-down heatmap
3D perception
BEVFormer · PointPillars · SMOKE
Large language models
Qwen2.5 / Qwen3 · DeepSeek-R1-Distill
Speech / ASR
Whisper
Vision-language-action
pi0.5 (SigLIP → LM → action)
1,309FPS
ResNet-50 · QC-Ultra
111FPS
ViT-Base · QC-Ultra
Live
per-model FPS/W & cycle detail
Scale-out
The same C++ and the same compiler target a single 64-PE QC-Nano core or eight 1,024-PE QC-Ultra cores. CGC generates the multicore code for you — tiling a large image across cores, batching inferences, or running heterogeneous workloads in parallel. Code written for one core runs at-speed on the rest.
Deploy
The core ships as synthesizable RTL. You profile on the ISS, validate in a SystemC virtual prototype of your SoC, and harden with reference Synopsys Fusion Compiler scripts for 7nm and 5nm — with safety-enhanced configurations built to ISO 26262 for automotive programs. The software you wrote on day one is the software that ships.
RTL
synthesizable source
Virtual prototype
ISS + SystemC
EDA
Synopsys · 7/5nm
Silicon
your SoC
ISO 26262
safety-enhanced
For developers
For architects