Scale workloads with one toolchain on Chimera™ GPNPU cores.

Chimera scales from a single core at 1 TOPS up to a 64-core multi-cluster solution capable of up to 6,912 TOPS.

Maximize performance by applying spatial, data, pipeline, or task parallelism across cores and workloads.

High resolution Vision in real time. Tile 4K images across cores for low-latency inference at full resolution.

Chiplet and multi‑chip ready. Easily bridge clusters across dies while using the same compiler‑managed toolchain.

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Chimera Core

Up to108TOPS

1 / 3

From 1 TOPS to 6,912 TOPS

Scale array size, add cores, bridge chiplets, all with the same software stack.

Chimera Core

Up to 108 TOPS per core

PE Count

8×8 → 16×16 → 32×32

Chimera QC-Multi

Up to 8 cores, up to 864 TOPS

Core Count

2 → 4 → 8

Chimera Multi-Cluster

Up to 64 cores, up to 6,912 TOPS

Cluster Count

2 → 4 → 8

MLSDirect L2↔L2 sharing between cores

Customer NoCCross-cluster interconnect

Four Ways to Scale Your Workload

Chimera GPNPU supports spatial, data, pipeline, and task parallelism: you choose the pattern that fits.

Spatial Parallelism

Tiling

Large input is partitioned into tiles, with adjacent cores exchanging edge data via MLS. Processing is done in parallel.

Best for: 4K+ images, low-latency inference

Data Parallelism

Batching

Run the same model on each core, processing different batches, with perfect scaling.

Best for: High throughput on smaller models

Pipeline Parallelism

Stages

Model layers are partitioned across cores as pipeline stages, maximizing weight bandwidth.

Best for: Large language models (8B–30B+)

Task Parallelism

MIMD

Each core runs a separate model or workload independently with no synchronization overhead.

Best for: Multiple independent workloads

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Chimera QC-Multi: Multicore Cluster

Homogeneous clusters of 2, 4, or 8 cores with direct L2↔L2 sharing.

QC-Multi

Key: MLS enables direct L2↔L2 access between cores; AXI Coalescer optimizes external memory bandwidth.

Hardware View

For Processor Architects

MLS Crossbar — Direct L2→L2 paths between all cores; any core reads/writes neighbor's L2
Software-Managed Memory — L2 is scratchpad (not cache), data movement is explicit
AXI Coalescer — Single DDR fetch, broadcast to all cores running same model
Independent AXI — Per-core bandwidth to system

Programming Model

For Software Architects

Producer-Consumer — Cores produce and consume data simultaneously
Explicit Sync — Hardware provides sync instructions, compiler manages coherency
No Manual Partitioning — Compiler handles data placement across cores

Multi-Cluster GPNPU System

Scale Chimera QC-Multi GPNPU clusters through your Network-on-Chip.

Multi-Cluster Architecture

How Multi‑Cluster Works

Component Overview

MLS Crossbar — Direct L2↔L2 sharing within each cluster
AXI Coalescer — Shared memory access, weight broadcasting
Customer NoC — System integrator's interconnect for cross-cluster communication

AXI Interfaces

Per Cluster

C-AXI — Control — host commands, status
M-AXI — MLS — cross-cluster L2 data sharing
I-AXI — Instruction — program fetch
D-AXI — Data — RAM access for weights/activations

From Edge to Autonomous Driving

TinyML / IoT

1× QC-Nano

Up to7TOPS

High-Volume Vision

2× QC-Perform

Up to28TOPS

Edge LLM

4× QC-Perform

Up to112TOPS

ADAS L2+

8× QC-Ultra (1 chiplet)

Up to864TOPS

Autonomous / L4+

64× QC-Ultra (8 chiplets)

6,912TOPS

8-Chiplet System Architecture

Scale Your AI Chip Ambition

Chimera scales from 1 TOPS edge devices up to 6,912 TOPS autonomous systems, all on the same architecture and software.

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~99% linear scaling efficiency

2-8 cores per QC-Multi

Up to 8 QC-Multi clusters for up to 64 cores

Scale workloads with one toolchain on Chimera™ GPNPU cores.

Chimera scales from a single core at 1 TOPS up to a 64-core multi-cluster solution capable of up to 6,912 TOPS.

Maximize performance by applying spatial, data, pipeline, or task parallelism across cores and workloads.

High resolution Vision in real time. Tile 4K images across cores for low-latency inference at full resolution.

Chiplet and multi‑chip ready. Easily bridge clusters across dies while using the same compiler‑managed toolchain.