Build AI on your own terms.

AI processor IP and software stack built to keep pace with your model roadmap.

One IP foundation

Inference from 1 to 6,912 TOPS.

One architecture

A sensor chip to a multi-die autonomy system.

One toolchain

Your models, compiled to any number of cores.

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Traditional edge AI silicon can’t keep up.

Traditional accelerators staple multiple blocks and toolchains together, with NPUs designed for yesterday's models, not tomorrow's.

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Chip delays. Multiple accelerator blocks, complex integration, and validation delay tapeout.

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Brittle silicon. Fixed‑function NPUs target today's operators, not tomorrow's.

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Fragmented toolchains. Different toolchains for each block have to be synchronized and debugged.

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Programmability time bomb. Rely on the vendor to port your new model and hope the silicon can support it at useful speed.

Or you could just use Chimera™ GPNPU.

One core. One toolchain. Unified, general-purpose inference.

Licensable processor IP for end-to-end inference that grows with you, with one toolchain for your entire chip line.

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Future flexibility. Fully programmable in C++, or use ChiPy® to orchestrate Python across the stack. New operators and model architectures map without a respin.

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Silicon efficiency. No hops between blocks mean higher perf-per-watt, lower latency, and a smaller silicon footprint.

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Software simplicity. Deterministic execution with one toolchain, one code stream, and no partitioning across accelerators.

Selected by DENSO for next-gen ADAS
2025 Edge AI & Vision Product of the Year

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Chimera SDK

Flexible development with Chimera™ SDK.

Auto-compile most models. Extend the rest in Python and C++.

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Fast porting. Chimera Graph Compiler (CGC) auto‑compiles hundreds of models, just import ONNX from PyTorch or TensorFlow and run.

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Self-service extensibility. Don't wait for Quadric for new ops, use C++ with the included LLVM compiler.

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Pre-silicon accuracy. Instruction Set Simulator (ISS) gives cycle‑accurate performance prediction before tape‑out.

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Multi-core. Multi-cluster. Multi-chip. Scale up.

Chimera cores can cluster across a die, chiplets, and chips. The compiler is built to spread one model across them without changing your code.

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1 to 6,912 TOPS. Chimera scales from a single core sub‑1W TinyML solution all the way up to a 64‑core multi-cluster capable of handling SAE L4 self‑driving.

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One model, many dies. Graph compiler-managed data, tensor, and/or pipeline parallelism across cores and dies.

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Near perfect linear scaling. ResNet-50, ViT, CenterNet, and MobileNetV2 show ~99% scaling from one to four cores.

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Datacenters have a ceiling. Local AI doesn’t.

The next billion AI users won't connect to a datacenter. They'll run inference locally on silicon built for it.

CONSUMER

AI in Your Hands

Multimodal AI running on PCs and mobile with voice, gesture, personalization, and privacy.

ENTERPRISE

Vision at Scale

Local servers and smart devices with inspection, security, and analytics where the data lives.

ROBOTICS

See, Think, Act

Multimodal perception and decision-making, with sensor fusion, navigation, and manipulation.

AUTOMOTIVE

Functional Safety

Real-time vision, radar, and LiDAR processing with ASIL B/D support, from in-cabin monitoring to full ADAS.

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Latest from Quadric

Blog

Oct 22, 2026

From Perception to Driving Actions: Alpamayo on Chimera

We mapped NVIDIA's Alpamayo 1.5, a 10-billion-parameter driving model that explains its decisions and plans a path, onto four Chimera GPNPU cores in W4A16. On held-out driving clips, it writes the same reasoning as NVIDIA's reference model, token for token. Our initial release will land in Chimera SDK 26.10, and we are already working to make it faster. We expect to get it to about 0.9 seconds per sample in subsequent releases.

Oct 17, 2026

Chimera Can Run DOOM. Can It Play It Too?

Chimera can render DOOM. Now we’ve trained a model to play from those frames, running on the same processor.

Oct 6, 2026

BEVFormer-Tiny on Chimera: Bird's-Eye-View Perception in One GPNPU Kernel

BEVFormer-Tiny runs its neural-network stages in one Chimera GPNPU kernel. Six camera inputs, 16.1 million cycles per frame in the four-core instruction-set simulator. Here’s how ChiPy brings the network together.

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News

Jul 14, 2026

Quadric Extends Series C to $46M with Second Close led by World Bank's IFC

Quadric announces the second close of its Series C, extending the round to $46M led by IFC (International Finance Corporation, World Bank Group), bringing total capital raised to $90M to support customers in automotive, AI PCs, humanoid robotics, wearables, and networking.

Jan 14, 2026

Quadric, Inference Engine for On-Device AI Chips, Raises $30M Series C as Design Wins Accelerate Across Edge LLMs, Automotive, and Enterprise

Tripling product revenues, comprehensive developer tools, and scalable inference IP for vision and LLM workloads, position Quadric as the platform for on-device AI.

Jan 14, 2026

Quadric's SDK Selected by TIER IV for AI Processing Evaluation and Optimization, Supporting Autoware Deployment in Next-Generation Autonomous Vehicles

Quadric today announced that TIER IV, Inc., of Japan has signed a license to use the Chimera AI processor SDK to evaluate and optimize future iterations of Autoware, open-source software for autonomous driving pioneered by TIER IV.

View all news

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AI belongs everywhere.

In datacenters, but also pockets, dashboards, factories, and devices you haven’t imagined yet. Quadric Chimera processors get it there.

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