Proved the innovative Chimera™ architecture by producing a test chip
Introduced industry's first licensable GPNPU (General Purpose Neural Processing Unit)
Began delivering production-ready Chimera processor IP to customers
Launched third-generation Chimera AI processors with automotive safety-grade variants
With more than 1,000 hardware configurations, there is a Quadric Chimera processor suited to every high‑volume inference application.
Quadric, Inc. is a semiconductor IP licensing company. We deliver blueprints for efficient, flexible AI processors to a wide range of customers designing chips for various frontier applications. Our licensees are both semiconductor companies who sell to broad user bases as well as systems companies designing chips for their own internal use. We focus on solutions for AI inference in devices and on the edge.
We have design wins spanning the industry's widest performance range, starting at 1 TOPS (Trillion Operations Per Second) to hundreds of TOPS. Those wins span markets including automotive ADAS systems, AI PCs, industrial sensors, robotics, office automation equipment, network processors, and more. Quadric addresses a broader Served Available Market (SAM) than competing IP licensors, priming us for broad adoption and market leadership.
The fully programmable nature of our Chimera processor is what distinguishes Quadric's General Purpose Neural Processing Unit (GPNPU) architecture from competing NPU accelerator solutions. Unlike NPUs that are programmed in idiosyncratic hardware command streams or hardware‑centric assembly code, Chimera GPNPUs are programmable using common AI graph formats, C++, and Python: languages known and used by millions of programmers worldwide.
Design Once, Update Forever: Smarter ROI in AI
The two key determinants of the return on investment in an AI‑enabled chip design are:
How many AI models can run at high performance on the device, including models not yet invented?
Can your team and downstream users easily port new models, or will you be forever dependent on the NPU vendor team to respond to market changes?
Designs which employ fixed-function AI accelerator blocks could be rendered useless by the next novel model architecture, but Quadric Chimera processors ensure support for models today and tomorrow.
No one can predict which new AI model will take the world by storm in three years, or five, or more, but with a Chimera processor powering your project's AI, you know your chip will be ready.
One Architecture for Every Layer: Solving Graph-Partitioning at the Source
Quadric is the only licensor of NPU solutions for accelerating edge AI that:
Quadric didn’t start with existing legacy compute blocks and bolt on a matrix accelerator.
Chimera’s single processor pipeline runs all three layers of AI models: matrix, vector, and scalar.
Chimera’s GPNPU processor core eliminates the AI graph partitioning, synchronization, and debug problems that handicap other NPU solutions.
Run every layer of every model on a single Chimera processor.
Artificial Intelligence (AI) enhances the functionality of devices used in many applications: autonomous vehicles, industrial robots, remote controls, game consoles, smartphones, networking hardware, and more. Machine Learning (ML) is a subset of the broader category of AI. By using ML models which are trained by sifting through enormous amounts of historical data to discover patterns, devices can perform amazing and complex tasks without being explicitly programmed.
ML models are created using known labeled datasets to discover patterns
Trained models make predictions when presented with new, unknown data in live deployment
Because training and inference are both highly specialized and computationally intensive, dedicated AI/ML compute resources are critical to handle those workloads.
For most high‑volume consumer products, chips are designed with tight cost, power, and size limitations. This is the primary (but not only) market Quadric serves with our innovative semiconductor intellectual property (IP) building blocks. Our Chimera processors were designed from first principles for AI processing, allowing companies to rapidly build leading‑edge SoCs and more easily write application code for those chips.
