Chimera is a market-leading licensable NPU IP product and the only fully programmable NPU IP core. License it into your SoC and ship AI products that handle any current and future operator or model with software updates instead of silicon respins.
Quadric defines Chimera as a GPNPU (General-Purpose NPU), the next evolution of the NPU. Programmable instead of fixed-function, more versatile than traditional accelerators and able to run all AI models with high performance. One unified, programmable core replaces the NPU IP, DSP, and companion CPU, running the complete AI pipeline with a single toolchain.
Chimera GPNPU: The fully programmable NPU IP.
Any operator or model (including custom kernels) runs via C++. When AI evolves, update the software instead of the silicon.
Standalone: no companion CPU or DSP required.
Traditional fixed-function NPU IP requires helper processors, but Chimera executes the entire AI pipeline on one core.
One toolchain, one binary.
Fixed-function NPU IP fragments workloads across multiple compilers and compute units, complicating debugging and synchronization. Chimera unifies everything under one core and SDK.
Future-proof by design.
New AI operators deploy as software updates and the SoC remains current through its product lifetime.
Scale up, scale down.
Chimera is customizable down to sub-1W or up to multi-core, multi-chiplet solutions, with multiple individually configurable components that let you design exactly the Chimera you need.
Fixed-function NPU IP was designed for the AI landscape of 2018. Chimera was designed to evolve.
There are plenty of NPU IP solutions, but only Chimera was built for today and tomorrow.
The simplest NPU IP, these are hardware blocks that attach to a legacy programmable processor and accelerate a very limited number of convolution operators found in common CNNs. The CPU does most of the work.
More capable NPU IP that implements dozens of graph operators in fixed-function hardware; fast for common AI workloads but requires a (typically much slower) programmable companion core for anything beyond its fixed operator set.
Chimera evolves the NPU to a General-Purpose NPU that executes any operator (including custom kernels) via C++. No companion CPU or DSP cores are required, and it supports current and future models with software updates instead of silicon respins.
Even NPU IP that supports dozens of operators falls short of the more than 2,300 unique operators found today. Chimera supports them all.
Chimera processors excel in applications that have long lifespans and need regular AI model updates.
L2+ perception, sensor fusion, and driver monitoring running on a single programmable NPU IP core.
Defect detection, quality inspection, and predictive maintenance at the edge.
Always-on object detection and tracking in power-constrained form factors.
Real-time navigation, obstacle avoidance, and scene understanding on custom silicon.
NPU IP (Neural Processing Unit Intellectual Property) is a licensable hardware block that semiconductor companies integrate into their SoCs to accelerate AI and machine learning workloads. Chip designers license NPU IP rather than design AI accelerators from scratch, reducing development cost and time-to-market.
Most NPU IP is fixed-function: it supports a predetermined set of AI operators and requires a companion CPU and DSP to handle the rest. Chimera is a GPNPU (General-Purpose NPU), 100% programmable via C++, with matrix (NPU), vector (DSP), and scalar (CPU) logic built into a single core. It runs complete AI workloads without companion processors and handles any operator (including custom and future AI operators) with software updates instead of silicon respins.
Quadric licenses Chimera as semiconductor IP. Chip companies receive RTL, verification IP, and the Chimera SDK under a standard IP license agreement. The Chimera GPNPU integrates into SoC designs like any other IP block, with full technical support from Quadric's engineering team through tape-out.
Chimera NPU IP targets always-on edge AI applications, including automotive ADAS, industrial machine vision, smart cameras, robotics, network processing, and consumer wearables. Any application requiring real-time neural network inference at low power on a custom SoC is a fit for Chimera.
No. Traditional NPU IP is just an accelerator offloading work from a host CPU, but it can't run a complete AI pipeline on its own. Chimera is a standalone processor able to execute the entire AI workload by itself, without requiring companion CPUs or DSPs for unsupported operators.
Chimera disproves the common misconception that edge AI requires heterogeneous solutions: NPU IP stitched to companion CPUs and DSPs.
Chimera offers a better way: one programmable GPNPU with one toolchain, able to run every model.
