Chimera is one of the market's leading licensable NPU IP products — and the only NPU IP core that is fully programmable. License it into your SoC and ship AI products that handle any model, any operator, any update, entirely in software.
Quadric refers to Chimera as a GPNPU (General-Purpose NPU) — an evolved class of NPU IP that is more versatile than traditional accelerators and runs all AI models in a highly performant manner. One programmable core replaces your NPU IP, companion CPU, and DSP, running the complete AI pipeline with a single toolchain.
Fully programmable NPU IP.
Any operator, any model — including custom kernels — via C++. No silicon respins when AI evolves.
Standalone: no companion CPU or DSP.
Traditional NPU IP needs helper processors. Chimera executes the complete AI pipeline on one core.
One toolchain, one binary.
Fixed-function NPU IP fragments workloads across multiple compilers. Chimera unifies everything under a single SDK.
Future-proof by design.
New AI operators deploy as software updates, not new silicon. Your SoC stays current through its entire product lifetime.
NPU IP Comparison
Fixed-function NPU IP was designed for the AI landscape of 2018. Chimera was designed for the one that keeps changing.
| Capability | Traditional NPU IP | Chimera GPNPU IP |
|---|---|---|
| Architecture | Fixed-function accelerator | Fully programmable GPNPU |
| Operator support | Predetermined list only | Any operator via C++ kernels |
| Companion processors | Requires CPU + DSP for full pipeline | Standalone — no companion needed |
| New AI models | May require silicon respin | Software update only |
| Toolchain | Multiple compilers per processor | Single Chimera SDK |
| Custom operators | Not supported | Native C++ kernel support |
The Spectrum of NPU IP
The NPU IP category spans a wide range of solutions. Understanding the differences is critical when evaluating what to license for your SoC.
The simplest NPU IP — hardware blocks that attach to a legacy programmable processor and accelerate only one or two types of convolution operators found in common CNNs. Minimal standalone value; the host CPU does most of the work.
More capable NPU IP that implements dozens of graph operators in a hardware state machine. Faster on common AI workloads, but still requires a companion programmable core for anything outside its fixed operator set.
Chimera. A fully programmable GPNPU that executes any operator — including custom kernels — via C++. No companion CPU or DSP required. Handles today's models and tomorrow's without a silicon respin.
Even NPU IP that supports several dozen operators falls dramatically short of the more than 2,300 unique operators found today in leading training frameworks such as PyTorch. When a complex AI model targets non-programmable NPU IP, the unsupported operators must run on the companion CPU, DSP, or GPU — a process known as Fallback.
Fallback causes dramatic declines in inference performance and often unacceptable increases in power dissipation, as data is constantly shuffled back and forth between the NPU IP and the companion programmable core. Chimera eliminates Fallback entirely — every operator runs on the GPNPU.
Applications
Chimera processors excel in applications that have long lifespans and need regular AI model updates.
L2+ perception, sensor fusion, and driver monitoring running on a single programmable NPU IP core.
Defect detection, quality inspection, and predictive maintenance at the edge.
Always-on object detection and tracking in power-constrained form factors.
Real-time navigation, obstacle avoidance, and scene understanding on custom silicon.
NPU IP (Neural Processing Unit Intellectual Property) is a licensable hardware block that semiconductor companies integrate into their SoCs to accelerate AI and machine learning workloads. Chip designers license NPU IP rather than design AI accelerators from scratch, reducing development cost and time-to-market.
Most NPU IP is fixed-function: it supports a predetermined list of AI operators and requires a companion CPU and DSP to handle the rest. Chimera is a GPNPU (General-Purpose NPU) — it is 100% programmable via C++, runs complete AI workloads on a single core, and handles any operator including custom and future AI ops without silicon respins.
Quadric licenses Chimera as semiconductor IP. Chip companies receive RTL, verification IP, and SDK under a standard IP license agreement. The Chimera GPNPU integrates into SoC designs like any other IP block, with full technical support from Quadric's engineering team through tape-out.
Chimera NPU IP targets always-on edge AI applications including automotive ADAS, industrial machine vision, smart cameras, robotics, and consumer wearables. Any application requiring real-time neural network inference at low power on a custom SoC is a fit for Chimera licensable NPU IP.
No. Traditional NPU IP is an accelerator — it offloads work from a host CPU but cannot run a complete AI pipeline on its own. Chimera is a standalone processor. It executes the entire AI workload, eliminating the need for a companion CPU or DSP to handle unsupported operators.
Chimera shatters the common misconception that edge AI requires heterogeneous NPU IP solutions stitched together with companion CPUs and DSPs. One programmable GPNPU. One toolchain. Every model.
Talk to Quadric's team about licensing Chimera NPU IP for your next SoC. We support licensees from architecture exploration through tape-out.
