The Chimera™ SDK compiles your model onto a single programmable core: the entire graph, not just the operators a fixed‑function block happens to support. New operators, custom kernels, and next year's architectures all run at native speed, because the compiler decides what runs, not the silicon.
Bring a trained ONNX model out of PyTorch or TensorFlow, quantize it with quadric_quantize, then compile, simulate, validate, and profile against a cycle‑approximate (±5%) model of the core, all within the Chimera SDK, on‑prem or in your cloud. No board required.
onnxquadric_quantizejob.compileISSprint(job)from tvm.contrib.epu.chimera_job.quantize import quadric_quantize
from tvm.contrib.epu.chimera_job.chimera_job import ChimeraJob
from tvm.contrib.epu.chimera_job.hw_config import HWConfig
q = quadric_quantize(
floating_point_model_path="model.onnx",
num_images=20, calibration_folder="./calib")
hw = HWConfig(product="QC-U", num_cores=4)
job = ChimeraJob(q.onnx_path, hw_config=hw)
job.compile() # CGC -> CCL C++ -> LLVM
job.run_inference_harness() # cycle-approximate ISS
job.validate_ort_iss() # accuracy vs ONNX Runtime
print(job) # FPS, power, MAC util, cyclesQuantized ≠ degraded
validate_ort_iss scores the simulator's INT8 output against ONNX Runtime's float output — on your model, before you commit. In our Whisper‑Tiny reference notebook that correlation is near‑perfect (0.9998); run the same check on yours and see the delta, not a promise.
The Chimera Graph Compiler (CGC) ingests your ONNX graph and does the hard parts for you: operator fusion, re-quantization rescheduling to hold precision where it matters, tensor layout across external / L2 / local memory, predictive weight prefetch, and multicore code generation.
CGC doesn't produce a sealed binary: it's human readable C++ built on our Chimera Compute Library (CCL). It's code you can open, run with a one-line CLI, and hand-tune. CGC is built on TVM and the datapath it targets is 100% programmable.
Chimera Graph Compiler — ONNX to Chimera ISA
Chimera Graph Compiler — ONNX to Chimera ISA
print(job) profile: latency, FPS, power, MAC utilization, and cycles.The hidden condition behind every “custom operators supported” footnote: On a fixed-function accelerator, an unsupported operator will either fall back to a CPU or DSP — risking being unusably slow in the process — or will require you to wait for the vendor to add it during their release cycle (if you're lucky.)
With Chimera, you don't have to wait for us: you can write the operator. Express it in C++ with the Chimera Compute Library, splice it into the graph with a few lines, and it runs at full speed on the same core as every native operator. No fallback and no waiting and hoping for support that might never come.
from tvm.contrib.epu import graphutils as gutils
replacer = gutils.CustomOpReplacer(onnx.load("model.onnx"))
subgraph, model = replacer.replace_subgraph(
output_nodes=["postprocess_output"],
input_nodes=["boxes", "scores"],
ccl_func_name="user::customPostProcess")// your kernel: full access to the PE array, LRM, DMA
template <typename T>
void customPostProcess(const T* in, T* out, size_t n) {
// runs native-speed on the same core as every op
...
}A traditional NPU freezes its operator set the day it's taped out and risks breaking on novel operators. But a Chimera core is a programmable processor: its model coverage grows with every compiler release and it never breaks on new models. That's borne out in our release history: code written for the prior generation QB core recompiles and runs on today's QC cores. Your software outlives silicon generations.
Llama-2
first LLM on the GPNPU
+ any-convolution support
ConvNeXt
QC-series target
detection + segmentation zoos
PointPillars
3D perception — LiDAR + monocular
+ classifier & OCR zoos
Qwen3-8B
+ DeepSeek-R1-Distill
billion-scale, 4-bit weights
Vision Transformer
Swin attention
+ deformable attention
pi0.5 VLA
vision-language-action
+ Whisper, BEVFormer 3D
The Chimera Instruction Set Simulator (ISS) included with the Chimera SDK models the whole core to within ±5%, with per‑workload power estimation and full state visibility. Run the Chimera ISS standalone to tune a kernel, or drop it into a SystemC virtual prototype of your full SoC to see real memory‑system behavior. It's not a black‑box engine build that changes its answer between runs: it's inspectable, deterministic, and repeatable.
Cycle breakdown
Determine where every cycle is used, whether it's compute, MAC, or data movement.
Average power
Get an accurate per-workload power estimate before tape-out.
External bandwidth
See how the compiler worked to avoid external memory traffic.
FILM region (fusion-in-local-memory)
Learn where intermediates were kept on-chip and off external memory.
Classifiers, detectors, segmentation, pose, 3D perception, vision transformers, LLMs, and vision‑language‑action stacks all compile from the same toolchain. Every benchmark is live, with FPS, FPS-per-watt, and a full cycle breakdown of each model and target, all regularly updated and available in Quadric's DevStudio.
Image Classification
ResNet · ViT · ConvNeXt · EfficientNet
Object Detection
YOLO · RetinaNet · FCOS · DETR
Segmentation
YOLOP · UNet · HRNet · FCN
Pose Estimation
RSN · top-down heatmap
3D Perception
BEVFormer · PointPillars · SMOKE
Large Language Models
Qwen2.5 / Qwen3 · DeepSeek-R1-Distill
Speech / ASR
Whisper
Vision-Language-Action
pi0.5 (SigLIP → LM → action)
1,309 FPS
ResNet-50 · QC-Ultra
111 FPS
ViT-Base · QC-Ultra
Live
per-model performance, perf-per-watt, and cycle detail
The same C++ and the same compiler can target a single 64‑PE Chimera QC‑Nano core, a QC‑Multi implementation of eight 1,024‑PE Chimera QC‑Ultra cores, or eight QC‑Multi configurations in a 64‑core multi‑cluster. Whether it's tiling a large image across cores, batching inferences, or running heterogeneous workloads in parallel, CGC generates the multicore code for you. Single-core code runs at-speed on the rest.
The core ships as synthesizable RTL. You profile on the Chimera ISS, validate a virtual prototype of your SoC in SystemC, and harden with reference Synopsys Fusion Compiler scripts for 7nm and 5nm, with optional safety‑enhanced configurations built to ISO 26262 for automotive programs. The software you wrote on day one is the software that ships.
RTL
Synthesizable Source
Virtual Prototype
ISS + SystemC
EDA
Synopsys · 7/5nm
Silicon
Your SoC
ISO 26262
Safety-Enhanced
For developers
For architects