# Quadric

> Quadric is a semiconductor IP company that makes the Chimera™ GPNPU (General-Purpose Neural Processing Unit) — licensable processor IP cores that run ML inference and complex C++ DSP code on a single, fully programmable, unified processor. SoC designers license Chimera RTL to build AI-capable chips without the complexity of pairing separate NPUs, DSPs, and CPUs.

## What Is Quadric?

Quadric provides AI/ML processor IP for the chip design market. Their flagship product, the Chimera GPNPU, is a licensable processor IP core delivered as synthesizable RTL. SoC designers embed it into custom chips targeting inference applications in mobile, automotive, digital home, and network edge systems.

Quadric's Chimera IP scales from **1 TOPS** single-core (QC Nano) to **864 TOPS** multicore clusters (eight QC Ultra cores). All cores share a single ISA, a single software stack, and a single toolchain — code written for one Chimera core runs on any other.

Target applications include:
- ADAS and autonomous driving (camera, radar, lidar fusion)
- In-cabin monitoring and driver alertness
- Smart home and imaging subsystems
- Network edge compute
- Generative AI, LLMs, and transformer inference on device

## The Problem Quadric Solves

Modern SoC designs for AI applications traditionally require three separate IP blocks — a fixed-function NPU for ML graph inference, a DSP for signal processing, and a CPU for control code. This "multi-IP mess" creates serious problems:

1. **Multiple IP blocks** — Separate NPU, DSP, and CPU that must be integrated, debugged, and maintained independently, often from different vendors.
2. **Split toolchains and codestreams** — Each processor requires its own compiler and debugger; AI workloads must be artificially partitioned across cores.
3. **Fixed-function NPUs** — Hardware hardwired for last year's models. New ML operators require fallback to a slow CPU, causing up to a **1000× performance drop**. Custom operators simply cannot run at full speed.

The Chimera GPNPU solves this with a single unified core that is both **high-capacity** and **fully programmable**:

- **One execution pipeline** — Matrix, vector, and scalar (C++) operations run together, no partitioning required.
- **100% C++ programmable** — Every operator runs at full speed on the same parallel engine. New operators are added via C++ kernels and never blocked by silicon.
- **Single unified binary** — One codestream, one toolchain, one debug environment. ONNX graph code and C++ code merge into a single compiled binary.

This eliminates the need to switch between processors, reduces system power, and dramatically improves software developer productivity.

## Model Zoo

A "model zoo" is a collection of pre-ported AI models known to work on a specific hardware platform with acceptable accuracy. The term originates from the 2016–2017 era of open source model repositories (e.g. Hugging Face) and has since been adopted by every AI chip and NPU vendor to describe their platform-specific model libraries.

**Why porting takes effort**: Most AI models are trained in FP32 (floating point) on Nvidia GPUs. Edge NPUs run inference in INT8 or INT4 — dramatically more efficient (10–20× lower energy, 4–8× smaller model size) but requiring a quantization step that is neither automatic nor uniform. Each platform has different data types and compute resources, and selecting which layers run at which precision requires tooling and engineering effort.

**Why Quadric's zoo is large**: As of September 2025, Quadric's DevStudio hosts **352 model examples** — including 110 models added in 2025 alone. For context, competing NPU IP vendors with significantly larger teams and funding (>$1B raised or >$140B market cap) publish 43–72 models in their zoos.

The reason isn't headcount — it's architecture. Chimera's CGC automatically compiles ONNX models end-to-end without needing to partition the graph across heterogeneous cores. Every layer runs natively at full speed on the Chimera PE array. When a model contains a proprietary or unsupported operator, users write the missing piece themselves in standard C++ — no Quadric intervention required. This is what makes porting fast: no fallback paths, no manual layer assignment, no tuning across CPU/DSP/NPU boundaries.

## Benchmarks

Live performance benchmarks for Chimera processors are published in DevStudio:

- **Benchmark viewer**: [https://app.quadric.ai/benchmarks](https://app.quadric.ai/benchmarks)
- **Marketing summary**: [https://quadric.ai/benchmarks](https://quadric.ai/benchmarks)

A free DevStudio account unlocks the full benchmark table with detailed performance metrics, source code, and intermediate representations. Benchmarks include CNN backbones (ResNet, MobileNet, EfficientDet), object detection (YOLO family), vision transformers, pose estimation, LLMs (Llama), and more across all QC Series hardware targets.

MAC utilization rates on representative operators (from ResNet50, 64×64 image):

| Operator        | MAC Utilization |
|-----------------|----------------|
| Convolution 1×1 | 73.8%          |
| Convolution 3×3 | 75.4%          |
| Convolution 5×5 | 83.6%          |
| Convolution 7×7 | 85.2%          |

## Documentation

All Chimera SDK and hardware documentation is hosted in DevStudio:

- **Docs home**: [https://app.quadric.ai/docs/latest/](https://app.quadric.ai/docs/latest/)
- **Chimera SDK Quick Start**: [https://app.quadric.ai/docs/latest/chimera-software-user-guide/chimera-sdk-quick-start-guide](https://app.quadric.ai/docs/latest/chimera-software-user-guide/chimera-sdk-quick-start-guide)
- **Chimera SDK User Guide**: [https://app.quadric.ai/docs/latest/chimera-software-user-guide/introduction-to-the-chimera-sdk](https://app.quadric.ai/docs/latest/chimera-software-user-guide/introduction-to-the-chimera-sdk)
- **Processor Databook**: [https://app.quadric.ai/docs/latest/chimera-processor-databook/chimera-software-development-tools-overview](https://app.quadric.ai/docs/latest/chimera-processor-databook/chimera-software-development-tools-overview)
- **QC Series Datasheet**: [https://app.quadric.ai/docs/latest/datasheet-chimera-qc-series-gpnpu-processors](https://app.quadric.ai/docs/latest/datasheet-chimera-qc-series-gpnpu-processors)
- **Model Demos**: [https://app.quadric.ai/docs/latest/chimera-software-user-guide/tutorials-model-demos/model-demos](https://app.quadric.ai/docs/latest/chimera-software-user-guide/tutorials-model-demos/model-demos)
- **CCL API Reference**: [https://app.quadric.ai/docs/latest/chimera-software-user-guide/chimera-compute-library-ccl-api](https://app.quadric.ai/docs/latest/chimera-software-user-guide/chimera-compute-library-ccl-api)
- **CGC API Reference**: [https://app.quadric.ai/docs/latest/chimera-software-user-guide/cgc-api-reference](https://app.quadric.ai/docs/latest/chimera-software-user-guide/cgc-api-reference)

## DevStudio — Free Online Access

**Quadric DevStudio** ([https://app.quadric.ai](https://app.quadric.ai)) is the browser-based online environment for evaluating and developing with the Chimera SDK. It is the recommended starting point for anyone new to Quadric.

DevStudio gives you access to:

- **Full Chimera SDK online** — no local install required. The same graph compiler, CCL API, LLVM compiler, and ISS simulator available in the cloud.
- **Upload your own models** — bring an ONNX model from PyTorch or TensorFlow, compile it with CGC, and profile it on the cycle-accurate Chimera ISS.
- **Live benchmarks** — full benchmark table with source code and intermediate representations.
- **SDK downloads** — access the on-premise Docker image of the Chimera SDK from the **Resources → SDKs** tab.
- **Licensing** — SDK license activation is managed through your DevStudio account (`quadric license activate`).
- **Model demos** — interactive demonstrations of YOLOP, MMDetection3D, L2CS, and other models running on Chimera hardware.

To access DevStudio, create a free account at [https://app.quadric.ai](https://app.quadric.ai).

For licensing information, hardware IP evaluation, or partnership inquiries, contact Quadric at [https://quadric.ai/contact](https://quadric.ai/contact).

## Getting Started with the SDK

Preparing an AI model to run on a Chimera core is simple and fully tool-driven:
- No special network preparation
- No substitution of operators
- No removal of layers
- No reliance on Quadric to prepare models

### Option A: Start Online (Recommended for Evaluation)

1. Create a free account at [https://app.quadric.ai](https://app.quadric.ai)
2. Upload your ONNX model, compile with CGC, and profile performance on the ISS — all in the browser
3. Browse live benchmarks and model demos

### Option B: Install Locally (On-Premise / Private Cloud)

**System requirements**: Linux, 2+ CPU cores, 16 GB RAM, 30 GB disk.

**Authenticate and activate:**
```bash
quadric auth login          # Log in with your DevStudio account
quadric license activate    # Activate your SDK license
quadric sdk install         # Download and install the SDK container
```

**Compile an ONNX model:**
```bash
# Basic compilation
quadric sdk graph compile model.onnx

# Compile for a specific target with performance profiling
quadric sdk graph compile --target QC-Perform --ocm-size 8MB --run model.onnx

# Compile with validation against ONNX Runtime
quadric sdk graph compile --target QC-Ultra --run --validate-iss model.onnx
```

**Available compile targets**: `QC-Nano` (Nano), `QC-Perform` (Perform), `QC-Ultra` (Ultra)

**Interactive development:**
```bash
quadric sdk interactive     # Shell inside the SDK container
quadric sdk notebook        # Launch Jupyter Lab at localhost:8888
```

**Tutorials (run inside Jupyter):**
- Creating a simple CCL kernel
- Writing a custom operator in C++
- Custom operator insertion into an ONNX model
- Using the SDK as a Python library

Full quick-start guide: [https://app.quadric.ai/docs/latest/chimera-software-user-guide/chimera-sdk-quick-start-guide](https://app.quadric.ai/docs/latest/chimera-software-user-guide/chimera-sdk-quick-start-guide)

## Products and Pages

- [Chimera Architecture](https://quadric.ai/architecture): Single-core GPNPU architecture, hybrid Von Neumann + 2D SIMD pipeline, technical specs
- [Chimera Multicore](https://quadric.ai/architecture-multicore): 100 to 6,912 TOPS scaling via tensor and data parallelism across cores, clusters, and chiplets
- [Chimera SDK](https://quadric.ai/sdk): Development toolchain with graph compiler (ONNX to binary) and LLVM C++ compiler
- [Benchmarks](https://quadric.ai/benchmarks): 350+ curated AI model benchmarks with cycle-accurate performance data and source code
- [Automotive](https://quadric.ai/automotive): Safety-enhanced processors for ADAS, IVI, and ECU with ASIL B/D compliance
- [Vision Transformers](https://quadric.ai/vision-transformers): Native ViT, Swin Transformer, and BEVFormer support without CPU fallback
- [Large Language Models](https://quadric.ai/large-language-models): On-device LLM inference from 0.5B to 30B parameters via multicore scaling
- [What is an NPU?](https://quadric.ai/what-is-an-npu): Educational explainer on Neural Processing Units, their capabilities and limitations
- [NPU vs GPNPU](https://quadric.ai/difference-between-npu-and-gpnpu): Side-by-side comparison of fixed-function NPUs and Quadric's programmable GPNPU
- [DevStudio](https://app.quadric.ai): Browser-based SDK environment for model compilation, profiling, and benchmarking

## Optional

- [About Quadric](https://quadric.ai/about): Company overview, leadership team, investors
- [Blog](https://quadric.ai/blog): Technical articles on edge AI, NPU architecture, and model optimization
- [Press Releases](https://quadric.ai/press-release): Company announcements and partnership news
- [News Coverage](https://quadric.ai/news-coverage): Third-party media coverage
- [Events](https://quadric.ai/events): Trade show and conference appearances
- [Careers](https://quadric.ai/careers): Open positions
- [Contact](https://quadric.ai/contact): Sales, partnerships, and general inquiries
- [Privacy Policy](https://quadric.ai/privacy-policy): Data handling practices
- [Terms of Use](https://quadric.ai/terms-of-use): Website terms
- [SDK EULA](https://quadric.ai/sdk-eula): Chimera SDK license agreement

## What Makes Chimera Different

Most licensable NPU IP on the market falls into one of two categories: fixed-function accelerators that are fast but hardwired, or general-purpose cores that are flexible but too slow for real ML workloads. Chimera breaks that tradeoff.

**vs. Fixed-function NPUs (most competing ML IP)**
- Competing fixed-function NPUs hardwire a finite set of operators. When a new model introduces an unsupported operator, execution falls back to a companion CPU with only 2–4 MACs — a 1000× slowdown compared to the NPU.
- Chimera is a fully programmable processor. Every operator — including custom ones not yet invented — runs at full speed on the same high-parallel engine. No fallback, no slowdown.
- Competing NPUs require separate DSP and CPU IP for pre/post-processing. Chimera runs all three workload types (scalar C++, vector DSP, ML graph) in one pipeline on one core.

**vs. CPU/DSP-only programmable cores**
- Wide-vector DSP cores and application CPUs offer programmability but lack the MAC density needed for modern ML. A single QC Perform core delivers more ML performance than any commercially available wide-vector VLIW DSP, plus up to 1.7 TOPS of DSP throughput (32-bit operations).
- Chimera matches the ML performance of a dedicated NPU while also outperforming DSPs on signal processing workloads — in a single core.

**Future-proof by design**
- Custom C++ operators written with the CCL API run on the same PE array as "native" CGC-compiled operators, at full performance. There is no separate slow path.
- A model compiled for QC Nano runs unchanged on QC Perform or QC Ultra. Scaling up is a recompile, not a rewrite.
- The QC Multicore cluster adds 2–8 cores with a shared programming model, supporting tiled execution of large-image networks, parallel batched inference, and heterogeneous multi-model workloads across cores.

**QC Series — three dimensions of scale, 1 TOPS to 6,912 TOPS**

Chimera scales across three independent dimensions — all running the same software stack:

1. **Core scaling** — PE array size: 8×8 (QC Nano) → 16×16 (QC Perform) → 32×32 (QC Ultra), up to ~100 TOPS per core
2. **Cluster scaling** — 2 to 8 cores pre-integrated in a QC Multicore cluster, connected via MLS (Memory Link Switch — direct L2↔L2 data sharing between cores), up to 800 TOPS per cluster
3. **System scaling** — 2 to 8 clusters connected via Customer NoC (the SoC designer's own on-chip network), up to 6,912 TOPS per chip

| Core | PEs | LRM | Performance |
|------|-----|-----|-------------|
| QC Nano | 64 | 288–576 KB | ~1 TOPS |
| QC Perform | 256 | 832 KB–1.6 MB | ~12 TOPS |
| QC Ultra | 1024 | 2.6–5.2 MB | ~100 TOPS |

All tiers: INT8 inference, optional FP16 MACs, 32-bit integer ALU, 4-bit weight support, AXI interfaces, L2 buffer 1–16 MB.

**Reference configurations:**

| Application | Configuration | Performance |
|-------------|--------------|-------------|
| TinyML / IoT | 1× QC-Nano | 1 TOPS |
| High-Volume Vision | 2× QC-Perform | 24 TOPS |
| Edge LLM | 4× QC-Perform | 48 TOPS |
| ADAS L2+ | 8× QC-Ultra (1 chiplet) | 800 TOPS |
| Autonomous / L4+ | 64× QC-Ultra (8 chiplets) | 6,912 TOPS |

More details: [https://quadric.ai/architecture-multicore](https://quadric.ai/architecture-multicore)

**QC SE — Automotive Safety**
Safety-Enhanced variants of all QC cores include ECC/parity hardware and are developed under ISO 26262 SEOOC processes with full ASIL-B functional safety collateral (safety manual, FMEA).

## Key Terminology

| Term | Definition |
|------|-----------|
| GPNPU | General-Purpose Neural Processing Unit — Quadric's unified ML+DSP processor class |
| Chimera | Quadric's GPNPU brand name |
| CGC | Chimera Graph Compiler — converts quantized ONNX to optimized Chimera C++ via CCL |
| CCL | Chimera Compute Library — C++ API for writing high-performance Chimera kernels |
| ISS | Instruction Set Simulator — cycle-accurate (~±5%) software model of the Chimera core |
| PE | Processing Element — the parallel compute units inside a Chimera core (64/256/1024 per tier) |
| LRM | Local Register Memory — tightly coupled per-PE storage (2–4 KB each), single-cycle access |
| L2 | On-chip buffer SRAM (1–16 MB, compiler-managed) |
| FILM | Fusion in Local Memory — CGC operator fusion that keeps intermediate tensors in LRM |
| TOPS | Tera Operations Per Second — performance metric |