# Quadric

> Quadric is a semiconductor IP company that makes the Chimera GPNPU (General-Purpose Neural Processing Unit) -- licensable processor IP cores that run ML inference and complex C++ DSP code on a single, fully programmable, unified processor. SoC designers license Chimera RTL to build AI-capable chips without the complexity of pairing separate NPUs, DSPs, and CPUs.

## What Is Quadric?

Quadric provides AI/ML processor IP for the chip design market. Their flagship product, the Chimera GPNPU, is a licensable processor IP core delivered as synthesizable RTL. SoC designers embed it into custom chips targeting inference applications in mobile, automotive, digital home, and network edge systems.

Quadric's Chimera IP scales from **1 TOPS** single-core (QC Nano) to **864 TOPS** multicore clusters (eight QC Ultra cores). All cores share a single ISA, a single software stack, and a single toolchain -- code written for one Chimera core runs on any other.

Target applications include:
- ADAS and autonomous driving (camera, radar, lidar fusion)
- In-cabin monitoring and driver alertness
- Smart home and imaging subsystems
- Network edge compute
- Generative AI, LLMs, and transformer inference on device

## The Problem Quadric Solves

Modern SoC designs for AI applications traditionally require three separate IP blocks -- a fixed-function NPU for ML graph inference, a DSP for signal processing, and a CPU for control code. This "multi-IP mess" creates serious problems:

1. **Multiple IP blocks** -- Separate NPU, DSP, and CPU that must be integrated, debugged, and maintained independently, often from different vendors.
2. **Split toolchains and codestreams** -- Each processor requires its own compiler and debugger; AI workloads must be artificially partitioned across cores.
3. **Fixed-function NPUs** -- Hardware hardwired for last year's models. New ML operators require fallback to a slow CPU, causing up to a **1000x performance drop**. Custom operators simply cannot run at full speed.

The Chimera GPNPU solves this with a single unified core that is both **high-capacity** and **fully programmable**:

- **One execution pipeline** -- Matrix, vector, and scalar (C++) operations run together, no partitioning required.
- **100% C++ programmable** -- Every operator runs at full speed on the same parallel engine. New operators are added via C++ kernels and never blocked by silicon.
- **Single unified binary** -- One codestream, one toolchain, one debug environment. ONNX graph code and C++ code merge into a single compiled binary.

This eliminates the need to switch between processors, reduces system power, and dramatically improves software developer productivity.

## Chimera GPNPU Architecture

Source: https://quadric.ai/architecture

The Chimera GPNPU is a hybrid Von Neumann + 2D SIMD matrix architecture that unifies matrix, vector, and scalar operations in a single execution pipeline. Unlike heterogeneous alternatives that require separate NPU, DSP, and CPU cores, Chimera operates as a single software-controlled core.

### Core Architecture

- 7-stage in-order pipeline
- 64-bit instruction word
- Scalar, vector, and matrix instructions with granular predication
- Deterministic, non-speculative execution (no branch prediction, no caches to flush)

### Memory System

- Distributed Local Register Memories (LRM) with data broadcast networks: 2-4 KB per PE, single-cycle access
- L2 data memory: 1 MB to 16 MB (compiler-managed SRAM buffer)
- Configurable instruction cache: 64/128/256 KB
- Configurable AXI interfaces for system integration
- Hierarchical memory minimizes DDR access -- data stays local

### Processing Capabilities

- Optimized for INT8 ML inference with optional FP16 MACs
- A8W4 (4-bit weight) support for memory-efficient inference
- 32-bit integer ALU for DSP operations
- Compiler-driven fine-grained clock gating for power efficiency
- Overlapped compute and data movement

### Three Pillars of Chimera

**System Simplicity**: A single core handles the entire AI/ML workload plus typical DSP functions and signal conditioning. This simplifies hardware integration, performance optimization, memory profiling, and power estimation. One core to integrate, one core to debug.

**Programming Simplicity**: Matrix, vector, and control code in a single codestream. Graph code from TensorFlow, PyTorch, or ONNX is compiled by the Chimera SDK and merged with C++ signal processing code into a single binary with a single debug console.

**Future-Proof Flexibility**: Chimera runs any AI/ML graph in ONNX plus any C++ code. New neural network operators and libraries can be written long after SoC tape-out. ML models evolve; Chimera's chip design cycles are future-proofed.

### GPNPU vs Traditional NPU

| Feature | Traditional NPU | Chimera GPNPU |
|---------|----------------|---------------|
| Programmability | Fixed-function hardware blocks | Fully programmable processor |
| New Operators | Requires silicon revision | C++ kernels post-deployment |
| Architecture | Requires CPU/DSP companion | Standalone unified core |
| Code Streams | Split across heterogeneous cores | Single unified codestream |
| Matrix Performance | High | High |

## Chimera Multicore Scaling

Source: https://quadric.ai/architecture-multicore

Chimera scales across three independent dimensions, all running the same software stack:

1. **Core scaling** -- PE array size: 8x8 (QC Nano) to 16x16 (QC Perform) to 32x32 (QC Ultra), up to ~100 TOPS per core
2. **Cluster scaling** -- 2 to 8 cores pre-integrated in a QC Multicore cluster, connected via MLS (Memory Link Switch -- direct L2-to-L2 data sharing between cores), up to 800 TOPS per cluster
3. **System scaling** -- 2 to 8 clusters connected via the SoC designer's own on-chip network (NoC), up to 6,912 TOPS per chip

### QC Series Processors

| Core | PEs | LRM | Performance |
|------|-----|-----|-------------|
| QC Nano | 64 | 288-576 KB | ~1 TOPS |
| QC Perform | 256 | 832 KB-1.6 MB | ~12 TOPS |
| QC Ultra | 1024 | 2.6-5.2 MB | ~100 TOPS |

All tiers: INT8 inference, optional FP16 MACs, 32-bit integer ALU, 4-bit weight support, AXI interfaces, L2 buffer 1-16 MB.

### Multicore Capabilities

- **Data parallelism**: Tiling splits 4K+ images across cores for high-resolution, real-time vision inference
- **Tensor parallelism**: Single-batch latency reduction for large models
- **Pipeline parallelism**: Multi-model workloads distributed across cores
- **LLM model parallelism**: Keeps latency tight as model size grows

### Reference Configurations

| Application | Configuration | Performance |
|-------------|--------------|-------------|
| TinyML / IoT | 1x QC-Nano | 1 TOPS |
| High-Volume Vision | 2x QC-Perform | 24 TOPS |
| Edge LLM | 4x QC-Perform | 48 TOPS |
| ADAS L2+ | 8x QC-Ultra (1 chiplet) | 800 TOPS |
| Autonomous / L4+ | 64x QC-Ultra (8 chiplets) | 6,912 TOPS |

### QC SE -- Automotive Safety

Safety-Enhanced variants of all QC cores include ECC/parity hardware and are developed under ISO 26262 SEOOC processes with full ASIL-B functional safety collateral (safety manual, FMEA).

## Automotive Solutions

Source: https://quadric.ai/automotive

Chimera Safety Enhanced (QC SE) processors are designed for automotive's most demanding applications. They combine accelerator efficiency with full C++ programmability for decade-long product lifecycles.

### Key Specifications

- Up to 864 TOPS multicore performance
- Up to 108 TOPS single-core
- ASIL B/D safety compliance
- 100% programmable

### The Automotive AI Dilemma

Automotive AI demands both extreme efficiency (for thermal constraints) and full flexibility (for decade-long lifecycles). Traditional solutions force a tradeoff:

**Data-center GPUs**: Fully programmable, run any AI model, but draw 100+ watts with impossible thermal profiles for automotive.

**Traditional NPUs**: Power efficient, automotive-grade thermal, but fixed-function hardware that cannot run new AI models.

**Chimera GPNPU**: Best of both worlds.
- 100% C++ programmable
- Runs any future AI model
- NPU-class power efficiency
- Automotive thermal profile
- ASIL B/D ready
- 12+ year lifecycle support

Whatever new AI networks emerge over the next decade, today's Chimera GPNPUs will run them with high performance, eliminating the risk of obsolescence that plagues fixed-function accelerators.

### Automotive Use Cases

- ADAS and autonomous driving (L2+ through L4+)
- In-vehicle infotainment (IVI) AI features
- Electronic Control Unit (ECU) consolidation
- Sensor fusion (camera, radar, lidar)
- In-cabin monitoring and driver alertness detection

## Chimera SDK

Source: https://quadric.ai/sdk

The Chimera SDK is the complete development toolchain for Chimera GPNPU processors. It provides the power of a code-driven processor with the convenience of no-code graph compilation.

### SDK Pipeline

1. **Inference Framework**: Import models from PyTorch or TensorFlow
2. **Graph Compiler (CGC)**: Automatic ONNX-to-binary compilation with optimization
3. **C++ Compiler (LLVM)**: Custom operator development via standard C++
4. **Binary**: Single unified executable
5. **SoC Deployment**: Run on any QC Series target

### Key Features

- **No-code graph compilation**: Import ONNX, compile, run. No operator substitution, no layer removal, no model preparation by Quadric.
- **Full C++ programmability**: Write custom operators in standard C++ using the CCL (Chimera Compute Library) API. They run at full PE array speed, not on a slow fallback path.
- **LLVM-based compiler**: Industry-standard toolchain for C++ kernel development
- **Cycle-accurate simulator (ISS)**: Instruction Set Simulator accurate to ~5%. What you simulate is what you get on silicon.
- **Single unified binary**: Graph code and C++ code merge into one binary, one debug console

### Getting Started

**Option A: Start Online (Recommended for Evaluation)**
1. Create a free account at https://app.quadric.ai
2. Upload your ONNX model, compile with CGC, and profile performance on the ISS -- all in the browser
3. Browse live benchmarks and model demos

**Option B: Install Locally**

System requirements: Linux, 2+ CPU cores, 16 GB RAM, 30 GB disk.

```
quadric auth login          # Log in with your DevStudio account
quadric license activate    # Activate your SDK license
quadric sdk install         # Download and install the SDK container
```

Compile an ONNX model:
```
quadric sdk graph compile model.onnx
quadric sdk graph compile --target QC-Perform --ocm-size 8MB --run model.onnx
quadric sdk graph compile --target QC-Ultra --run --validate-iss model.onnx
```

Available compile targets: QC-Nano (Nano), QC-Perform (Perform), QC-Ultra (Ultra)

Interactive development:
```
quadric sdk interactive     # Shell inside the SDK container
quadric sdk notebook        # Launch Jupyter Lab at localhost:8888
```

Tutorials (run inside Jupyter):
- Creating a simple CCL kernel
- Writing a custom operator in C++
- Custom operator insertion into an ONNX model
- Using the SDK as a Python library

Full quick-start guide: https://app.quadric.ai/docs/latest/chimera-software-user-guide/chimera-sdk-quick-start-guide

## Benchmarks

Source: https://quadric.ai/benchmarks

Quadric publishes transparent, validated AI model benchmarks in DevStudio. No tricks, no operator substitutions. Every benchmark runs the complete network graph with validated accuracy.

### Benchmark Library

- **350+** curated AI models with validated accuracy metrics
- **6** model categories: CNNs, Vision Transformers, LLMs, object detectors, segmenters, and more
- **100%** source access: full end-to-end graphs, intermediate representations, and source code

### Live Access

- Benchmark viewer: https://app.quadric.ai/benchmarks
- Marketing summary: https://quadric.ai/benchmarks

A free DevStudio account unlocks the full benchmark table with detailed performance metrics across all QC Series hardware targets.

### Model Categories

Benchmarks include CNN backbones (ResNet, MobileNet, EfficientNet, ConvNeXt), object detection (YOLO family, EfficientDet), vision transformers (ViT, Swin, DeiT), pose estimation, segmentation, LLMs (Llama), and more.

### MAC Utilization (ResNet50, 64x64 image)

| Operator | MAC Utilization |
|----------|----------------|
| Convolution 1x1 | 73.8% |
| Convolution 3x3 | 75.4% |
| Convolution 5x5 | 83.6% |
| Convolution 7x7 | 85.2% |

### Model Zoo

As of September 2025, Quadric's DevStudio hosts 352 model examples, including 110 models added in 2025 alone. Competing NPU IP vendors with significantly larger teams and funding (>$1B raised or >$140B market cap) publish 43-72 models in their zoos.

The reason is architecture: Chimera's CGC automatically compiles ONNX models end-to-end without needing to partition the graph across heterogeneous cores. Every layer runs natively at full speed on the Chimera PE array. When a model contains a proprietary or unsupported operator, users write the missing piece themselves in standard C++.

## Large Language Models on Chimera

Source: https://quadric.ai/large-language-models

Chimera GPNPU enables on-device LLM inference from 0.5B to 30B parameters. Multicore clusters scale seamlessly from single-core edge deployments to multi-die chiplet configurations.

### LLM Scaling

| Configuration | Parameters | Use Case |
|--------------|------------|----------|
| Single Core | Up to 1B | TinyML, edge assistants |
| Multi-Core | Up to 8B | On-device chat, code generation |
| Chiplet | Up to 8B | High-throughput inference |
| Multi-Chiplet | Up to 30B | Autonomous systems, robotics |

Same software scales across all configurations. Model parallelism keeps latency tight as models grow.

### Why Chimera for LLMs

- Full attention mechanism support (no operator fallback)
- INT8 and INT4 weight quantization for memory efficiency
- Compiler-managed memory tiling across cores
- Customer-validated, production-ready edge inference

## Vision Transformers on Chimera

Source: https://quadric.ai/vision-transformers

Chimera GPNPU delivers full Vision Transformer support, including attention mechanisms, LayerNorm, and GELU, without the operator limitations of legacy NPUs. No CPU fallback required.

### Supported Capabilities

- Any attention mechanism (multi-head self-attention, cross-attention)
- Any normalization (LayerNorm, BatchNorm, GroupNorm)
- Any activation (GELU, SiLU, Swish, Softmax)
- No CPU fallback for any operator

### Supported Model Families

- ViT (Vision Transformer): 86M parameters, 17.6 GFLOPS, 100% runs on Chimera
- Swin Transformer: Shifted-window attention for efficient high-resolution vision
- BEVFormer: Bird's-eye view transformers for autonomous driving perception
- DeiT: Data-efficient image transformers

### The Legacy NPU Problem with Vision Transformers

Traditional fixed-function NPUs were designed for CNN workloads (convolutions, pooling). Vision Transformers introduce operators that most NPUs do not support natively: multi-head self-attention, LayerNorm, GELU activation, dynamic reshaping. When these operators hit an NPU, execution falls back to a companion CPU with drastically lower throughput.

Chimera GPNPU is fully programmable. Every operator, including attention and normalization, runs at full speed on the PE array. There is no fallback path.

## What Is an NPU?

Source: https://quadric.ai/what-is-an-npu

An NPU (Neural Processing Unit) is a specialized hardware block used in semiconductor chip design to accelerate the performance of machine learning and artificial intelligence workloads. NPUs are optimized for the mathematical operations, particularly matrix multiplications, that form the foundation of neural networks.

### Why NPUs Were Created

Around 2015, chip designers recognized that emerging AI and machine learning algorithms would not run efficiently on existing processors. Neural networks rely heavily on matrix multiplication. Traditional processors (CPUs, GPUs, DSPs) handle these operations inefficiently for edge deployment. NPUs emerged as dedicated accelerators that execute AI inference orders of magnitude faster while consuming less power.

### How NPUs Work

NPUs accelerate four key operation types:
1. **Matrix Multiplication**: Dense matrix operations at the heart of neural networks
2. **Convolution Operations**: Efficient execution of convolutional layers for image recognition and computer vision
3. **Activation Functions**: Hardware support for ReLU, sigmoid, softmax
4. **Pooling Layers**: Accelerated max and average pooling for dimensionality reduction

### NPU System Architecture

A typical SoC with an NPU contains:
- **Host CPU**: Control, coordination, and execution of unsupported operators
- **NPU**: Accelerates matrix operations and supported neural network layers
- **DSP**: Signal processing (audio, sensor data, filtering)
- **GPU**: Graphics rendering and parallel compute

The NPU accelerates specific operations offloaded from the host CPU. The CPU coordinates the overall workload and handles any operations the NPU does not support.

### NPU Limitations

1. **Fixed Operator Set**: NPUs support a predetermined set of operations. When new AI research introduces novel operators, NPUs cannot execute them. New operators require silicon updates.
2. **Accelerator Architecture**: NPUs work alongside host CPUs and cannot execute complete AI workloads independently. Complex control flow and unsupported operators must run on the CPU.
3. **Partitioned Workloads**: Complex models must be split across NPU, CPU, and DSP cores, adding integration complexity and increasing power consumption.
4. **Multiple Toolchains**: Each processor in the system requires its own compiler, debugger, and development workflow.

### The Fixed-Function Degradation Problem

- **Supported model**: 95% runs on NPU (fast)
- **Model with new operators**: 60% NPU, 40% falls back to CPU (mixed performance)
- **Future model**: 20% NPU, 80% falls back to CPU (slow)

As AI research produces new architectures and operators, fixed-function NPUs execute an ever-smaller fraction of each model at full speed.

### From NPU to GPNPU

The GPNPU (General-Purpose NPU) is the next evolution:

| Aspect | Traditional NPU | GPNPU |
|--------|----------------|-------|
| Architecture | Fixed-function accelerator | 100% programmable processor |
| Execution | Requires companion CPU/DSP | Standalone execution |
| New operators | Requires new silicon | C++ kernels, software update |
| Model support | Limited to built-in operators | Any operator, any model |

## NPU vs GPNPU: Detailed Comparison

Source: https://quadric.ai/difference-between-npu-and-gpnpu

### Quick Definitions

**NPU**: A fixed-function hardware accelerator designed to speed up matrix operations for AI inference. Works alongside CPUs and DSPs but cannot execute complete workloads independently.

**GPNPU**: A fully programmable processor that combines NPU-class tensor performance with CPU-like flexibility. Executes entire AI workloads independently and adapts to new models via software.

### NPU Limitations

1. **Fixed-Function Hardware**: Built with predetermined operators optimized for specific AI models. When new algorithms emerge, the hardware cannot adapt.
2. **Requires Companion Processors**: Works as an accelerator paired with CPUs or DSPs. Complex workloads must be partitioned across multiple cores.
3. **Multiple Toolchains**: Each processor requires its own compiler, debugger, and codestream. Integration complexity multiplies with each added core.
4. **Silicon Lock-In**: New operators require new silicon. Chip capabilities are frozen at tape-out.

### GPNPU Advantages

1. **100% C++ Programmable**: Add new operators via software kernels after deployment. No silicon changes required.
2. **Standalone Execution**: Runs entire AI/ML workloads independently without companion processors. One core does it all.
3. **Unified Toolchain**: Single compiler, single debugger, single binary. ONNX graphs and C++ code merge seamlessly.
4. **Future-Proof Design**: Support tomorrow's models on today's silicon. The chip evolves with AI innovation.

### Side-by-Side Comparison

| Aspect | Traditional NPU | GPNPU |
|--------|----------------|-------|
| Architecture | Fixed-function accelerator | Fully programmable processor |
| Programmability | Limited to built-in operators | 100% C++ programmable |
| New Operators | Requires new silicon | Software update |
| Companion CPU/DSP | Required | Not required |
| Toolchains | Multiple (one per processor) | Single unified toolchain |
| Debug Environment | Multiple debug consoles | Single debug console |
| Future Models | May not support | Always supported |

### Why It Matters for SoC Design

AI models evolve faster than silicon design cycles. A chip taped out today must run models that do not exist yet. Fixed-function NPUs create risk: if a new model requires unsupported operators, performance falls back to legacy processors or the chip becomes obsolete. GPNPUs eliminate this risk through full C++ programmability, with new operators deployable via software, including over-the-air updates.

## DevStudio -- Free Online Access

Source: https://app.quadric.ai

Quadric DevStudio is the browser-based online environment for evaluating and developing with the Chimera SDK. It is the recommended starting point for anyone new to Quadric.

DevStudio gives you access to:

- **Full Chimera SDK online** -- no local install required. The same graph compiler, CCL API, LLVM compiler, and ISS simulator available in the cloud.
- **Upload your own models** -- bring an ONNX model from PyTorch or TensorFlow, compile it with CGC, and profile it on the cycle-accurate Chimera ISS.
- **Live benchmarks** -- full benchmark table with source code and intermediate representations.
- **SDK downloads** -- access the on-premise Docker image of the Chimera SDK from the Resources tab.
- **Licensing** -- SDK license activation is managed through your DevStudio account.
- **Model demos** -- interactive demonstrations of YOLOP, MMDetection3D, L2CS, and other models running on Chimera hardware.

To access DevStudio, create a free account at https://app.quadric.ai

## Documentation

All Chimera SDK and hardware documentation is hosted in DevStudio:

- [Docs home](https://app.quadric.ai/docs/latest/): Full documentation index
- [Chimera SDK Quick Start](https://app.quadric.ai/docs/latest/chimera-software-user-guide/chimera-sdk-quick-start-guide): Get running in minutes
- [Chimera SDK User Guide](https://app.quadric.ai/docs/latest/chimera-software-user-guide/introduction-to-the-chimera-sdk): Complete SDK reference
- [Processor Databook](https://app.quadric.ai/docs/latest/chimera-processor-databook/chimera-software-development-tools-overview): Hardware architecture details
- [QC Series Datasheet](https://app.quadric.ai/docs/latest/datasheet-chimera-qc-series-gpnpu-processors): Specifications for all QC tiers
- [Model Demos](https://app.quadric.ai/docs/latest/chimera-software-user-guide/tutorials-model-demos/model-demos): Interactive model demonstrations
- [CCL API Reference](https://app.quadric.ai/docs/latest/chimera-software-user-guide/chimera-compute-library-ccl-api): C++ kernel development API
- [CGC API Reference](https://app.quadric.ai/docs/latest/chimera-software-user-guide/cgc-api-reference): Graph compiler API

## Key Terminology

| Term | Definition |
|------|-----------|
| GPNPU | General-Purpose Neural Processing Unit -- Quadric's unified ML+DSP processor class |
| Chimera | Quadric's GPNPU brand name |
| CGC | Chimera Graph Compiler -- converts quantized ONNX to optimized Chimera C++ via CCL |
| CCL | Chimera Compute Library -- C++ API for writing high-performance Chimera kernels |
| ISS | Instruction Set Simulator -- cycle-accurate (~5%) software model of the Chimera core |
| PE | Processing Element -- the parallel compute units inside a Chimera core (64/256/1024 per tier) |
| LRM | Local Register Memory -- tightly coupled per-PE storage (2-4 KB each), single-cycle access |
| L2 | On-chip buffer SRAM (1-16 MB, compiler-managed) |
| MLS | Memory Link Switch -- direct L2-to-L2 data sharing between cores in a multicore cluster |
| FILM | Fusion in Local Memory -- CGC operator fusion that keeps intermediate tensors in LRM |
| TOPS | Tera Operations Per Second -- performance metric |
| QC-Nano | QC Nano: 64 PEs, ~1 TOPS |
| QC-Perform | QC Perform: 256 PEs, ~12 TOPS |
| QC-Ultra | QC Ultra: 1024 PEs, ~100 TOPS |
| QC SE | Safety-Enhanced variant with ISO 26262 ASIL-B collateral |

## Contact

For licensing information, hardware IP evaluation, or partnership inquiries: https://quadric.ai/contact